A 6.25Gbps Adaptive Decision Feedback Equalizer for Serial Data Link in 0.18µm CMOS Technology

This paper presents a 6.25Gbps adaptive 2-tap decision feedback equalizer (DFE) for serial backplane receiver. The proposed DFE can be used to reduce the effects of inter-symbol interference (ISI) and compensate the loss of the limited bandwidth channel. To meet the high speed requirement, the DFE is constructed in a half rate structure and most of the module such as MUX, adder and D Flip Flop are designed in current mode logic (CML). Additionally, an adaptation engine based on modified LMS algorithm is implemented, including sense amplifiers, a 6-bit up/down counter and a 6-bit DAC. The DFE has been implemented in 0.18 μm CMOS technology and the whole circuit area including pads is 600 × 550 μm
²
. Post-simulation results show that it can work properly at 6.25bps. The equalized eye opening can be larger than 0.8UI and power consumption is about 21 mW at 1.8 V supply voltage.