Joint Estimation of Propagation Delay Dispersion and Time of Arrival in a 40-nm CMOS Comparator Bank for Time-Based Receivers

This brief presents an approach to compensate time-of-arrival (ToA) estimation errors caused by the effect of signal depending propagation delays in receivers for ranging applications. As a straightforward reasoning, reducing the ToA error results in increased power consumption in the analog-front-end blocks of such receivers. In the proposed system topology, the asynchronous receiver's analog-front-end blocks contain an array of identical continuous-time comparators, which makes it suitable for a joint modeling approach and today's low-supply voltages. Attention is paid to tuning the nonstrobed comparator topology to make it suitable for this joint modeling. Using the comparator model in a least-squares-based algorithmic approach can reduce the ToA error (accuracy improvement) to nearly zero. A ToA systematic error reduction of 28 is faced for the ToA figure. Furthermore, energy consumption is more related to the activity of the ranging events, which makes this an interesting approach for ranging measurement rates of less than 1 MHz.