Effect of electrical stress on the Al2O3-based 4H-SiC MOS capacitor with a thin SiO2 interface buffer layer

The effect of electrical stress on the Al
₂
O
₃
-based n-4H-SiC metal oxide semiconductor (MOS) capacitor with a thin SiO
₂
interfacial buffer layer (IBL) has been investigated. The electrical characteristics of MOS capacitors have been measured using capacitance-voltage (C-V), current-voltage (I-V) and charge trapping behavior of the films under constant voltage stressing (CVS) to understand the reliability and the interface trapping characteristics of Al
₂
O
₃
/SiO
₂
/n-4H-SiC gate stack. It is found that Al
₂
O
₃
/SiO
₂
stack layer has lower positive charge generation and smaller flatband voltage shift under constant voltage stressing, which exhibits an excellent interface quality and high dielectric reliability making this structure suitable for 4H-SiC power devices applications.