A methodology and algorithms for efficient interprocess communication synthesis from system description in SDL

This paper discusses a methodology and algorithms for efficient hardware synthesis of inter-process communication in systems described in SDL. The basic idea of our approach is to implement an SDL process by two hardware blocks, namely Computation Block and Communication Block. The Computation Block implements the data computation functions of the process as an Extended FSM (EFSM). The Communication Block implements the communication of the process with other processes. We give an algorithm to classify the communication requirements of the process and have an efficient implementation for it. Our scheme also has a supervisor block for every SDL block to manage interprocess communication. Our methodology supports multiple instances of the processes and dynamic processes. In our scheme, a single copy of hardware (Compute block) is shared among multiple copies of a process within a block which leads to efficient hardware implementation.