Analysis of ESD protection circuits for high — Performance CMOS structures

Due to the low breakdown voltage of the gate oxide in CM OS technologies, highly effective Electrostatic Discharge (ESD) protection designs should be implemented in each device technology. Therefore, innovative protection designs were investigated in order to increase the high - precision and robustness of the integrated CMOS structures. The paper aims to create the context in which the proposed designs achieve an effective protection by reducing the high-currents, when ESD voltage pulses of fast rise time are applied at the inputs of the circuits.