Ultra-low voltage drain-bulk connected MOS transistors in weak and moderate inversion

This paper aims to demonstrate the basic characteristics of NMOS and PMOS drain-bulk connected transistors for ultra-low voltage applications. On-wafer measurements were done on 180nm CMOS process, while TCAD simulations were done for 180nm and 45nm technology nodes. Analytical expressions for Early voltage and intrinsic gain in weak-moderate inversion are provided, showing that these quantities are dominated by the substrate effect and are insensitive to bias and geometry. Furthermore, the analytical model as well as the EKV3 MOSFET compact model, following suitable parameter extraction, show a close agreement to measured and TCAD simulated data.