Conflict free, parallel memory access for radix-2 FFT processors

The current paper presents a parallel addressing technique for radix-2 FFT architectures. The novel technique bases on a permutation to accomplish parallel load and store of the FFT data even with a single memory bank, which stores two FFT elements at each address. Furthermore, the proposed addressing scheme minimizes the requirements for the address generation and processor control circuits. An example FPGA implementation shows the simplicity of the architecture and validates the results.