HotSpot minimization using fine-grained DVS architecture at 90 nm technology

Power and temperature has become the major design challenges in the development of today's complex low power digital integrated circuits due to the adverse effect of these parameters on performance, reliability, cooling and packing costs, as well as increase in leakage power as we gradually move towards deep submicron technology. The increasing adoption of fine-grained power management strategies in design synthesis flow has motivated us to build power and temperature conscious designs using such strategies at the behavioral level. In this paper, we propose power and temperature aware multi-objective scheduling and binding algorithms during behavioral synthesis stage using fine-grained dynamic voltage scaling enabled functional units to alleviate the problem of localized heating, which often leads to hotspot zones in chips.