"Depletion isolation effect" of surrounding gate transistors

Sub-half-micron surrounding gate transistors (SGTs) were fabricated and their current-voltage (I-V) characteristics were investigated. Even in a SGT whose Si pillar is not fully depleted (e.g., 0.6 /spl mu/m SGT), by using the lower diffusion layer of the Si pillar as drain and applying sufficiently high voltage, I-V characteristics inherent to fully depleted devices (i.e. subthreshold swing as low as 60 mV/dec., lowered threshold voltage independent of substrate bias voltage) were observed ("depletion isolation effect").