VLSI implementation of 2-D discrete wavelet transform for real-time video signal processing

This paper presents the architecture and implementation of a single-chip VLSI for the two-dimensional discrete wavelet transform (2-D DWT) decomposition. This nonseparable based architecture uses a parallel-systolic filter structure to compute all the resolution levels of the DWTs, such that the input samples can be processed at the rate of one sample per clock cycle. The chip was fabricated in a 0.6 /spl mu/m CMOS technology and packaged as a 48-pin DIP. For the computation of an N/spl times/N still image with a filter length L, this chip needs N/sup 2/+N clock cycles and N(2L-1) memory storage; for continuous picture such as video signal, its average computation time per picture is about N/sup 2/ only.