A 60GHz power amplifier using high common-mode rejection technique

This paper proposes the method of realization of high common-mode rejection ratio(CMRR) at 60 GHz. High CMRR can compensate the differential mismatch. In the proposed method, virtual ground for differential-mode and LC peaking for common-mode are utilized. To confirm the effect of this technique, the 2-stage differential power amplifier is fabricated in a 65nm CMOS process. It achieves a CMRR of 26 dB, a power gain of 12.1 dB, a peak PAE of 11.1%, a P
_sat
of 9.0 dBm, a power consumption of 45.8mW from a 1.0V power supply.