A low power, high speed, IF range Flash Type ADC designed with the concept of TMCC and Binary Counter

In this paper the implementation of a low power high speed 3-bit Flash Type ADC is reported using 180 nm CMOS technology. The concept of Threshold Modified Comparator Circuit (TMCC) is introduced as a modification of the conventional comparator. The reported structure of the ADC occupies an active area of 0.012 mm
²
and consumes 179 μWatt of Average Power while operating with an input frequency (f
_in
) of 10 MHz, and a supply voltage of 1.8Volt. This fin can further be increased to a value of 15 MHz, yielding the Average Power consumption of 209 μWatt. For this proposed architecture, the maximum sampling rate is obtained as 0.044 GSPS. At 0.044 GSPS sampling rate, the Signal to Noise plus Distortion Ratio (SNDR) is found to be 19.82 dB.