Low power unsigned integer multiplier for digital signal processors

Computational architectures for signal processing applications involve extensive use of multipliers. Operations in image processing like image sharpening, smoothing, feature extraction, segmentation etc involve large number of multiplications. Embedded computational architectures for such systems require low power design with minimal trade off in speed and area. Multiplier architectures proposed in literature seek to reduce power dissipation by reduction of effective switching activity or reduction in effective switched capacitance. Some of the architectures seek pre-computation as an area trade off for power. We propose a architecture for unsigned integer multiplication intended to be used in implementation of data path for real time image processing. The multiplier is based on divide and conquers approach, which provides significant reduction in power dissipation if the inputs are from a source of correlated data as compared to regular array based multipliers. Such inputs are common in signal processing where the inputs are samples of real world signals from a sensor. We characterize a family of unsigned integer multiplier architectures by considering three multipliers for each of the 8, 16 and 32 bit word length cases and compare their performance against the Array and Wallace multiplier architectures used for similar class of applications. It has been observed in our experiments that the proposed multiplier can have a power advantage of up to 34.92% as compared to Array multiplier when subjected to image data, with equal area characteristic and a very marginal trade off in speed.