A novel quantization algorithm suitable for high-speed analog-to-digital converters

A novel quantization algorithm capable of being employed in high-resolution high-speed ADCs is described. In order to verify the efficiency of proposed architecture a 3.3-V 10-bit ADC with roughly 67-dB spurious free dynamic range (SFDR) and 59-dB signal-to-noise-and-distortion ratio (SNDR) has been reported. The converter designed in standard 0.35-μm CMOS technology consumes 156 mW from a nominal supply voltage when it operates at a sampling rate of 80-Msample/s.