Hydrogen silsesquioxane as a gate dielectric layer for SiC graphene FET

Graphene can be prepared by annealing of SiC wafer. That allows large scale patterning by standard UV photolithography. Unfortunately SiC substrate does not allow backgating in contrast to graphene on silicon substrate (with thin silicon dioxide layer). The major challenge is to find suitable dielectric layer that can be used for electrostatic gating without significant influence on carrier mobility or another properties of graphene. We examined electrical behavior of electron exposed hydrogen silsesquioxane (HSQ) layer used as dielectric layer of topgated SiC graphene. We prepared seven sets of capacitor structures for test of HSQ layer electrical properties. The capacitors have different dimensions (100x5 - 100x100 μm) and each set had different exposure energy (12 - 480μC/cm
²
) and annealing process. Electrodes and contacts were prepared by evaporation of 3/30 nm thick Cr/Au layer. The influence of exposure energy to electrical properties of HSQ layer was observed. The dimension of capacitor structures had lower effect than exposure energy. The gated Hall-bar structure of SiC graphene will be prepared subsequently. Hall-bar will be defined by e-beam lithography, etched by oxygen plasma and contacted by evaporation. HSQ will be used as a gate dielectric.