Frame assembly and scheduling on edge routers in fixed-size frame-switching networks

Frame assembly is seen as an important technology in future core networks since it can mitigate the ever-increasing packet header processing load on network nodes. Since frame assembly changes the pattern of traffic entering the network, it has a significant impact on such aspects of network performance as packet drop probability and end-to-end delay. This paper focus on the packet drop and delay performance on assembly nodes, sometimes called edge routers. We reveal that frame assembly on edge routers is in fact a tradeoff between packet loss performance and fairness, especially when the input client traffic is non-uniformly distributed among multiple destinations. We evaluate existing frame assembly and scheduling algorithms and try to cope with the assembly and scheduling process holistically by proposing a new algorithm, named highest efficiency fair queuing. Simulation results show that the proposed algorithm provides better performance in terms of delay and jitter, while also minimizing the average packet loss rate.