Survey and analysis of 0.18 urn CMOS integrated antennas on 5.8 GHz for RFD

The issue of major interest during RFID systems development is reducing the size and price of RFID tag. This article is dedicated to design and implementation of 0.18 um CMOS integrated antenna for RFID system to include price of antenna implementation in price of RFID IC. Decreasing techniques of influence of layout configuration and methods of decreasing of metal stress states inside chip on antenna parameters are discussed. Functional synchronization was used in the generator to provide 5725 ÷ 5875 MHz differential output signal with 1.8 V supply voltage. Test antenna was implemented within test die, size 5×5 mm
²
, 0.18 um CMOS technology. A possibility of further decreasing of antenna size up to 1 mm2 was analyzed. Implemented antenna has gain of -25 dB@5.8 GHz and could be used up to 9 GHz without significant loss in efficiency.