Efficient SIMD optimization of HEVC encoder over X86 processors

High Efficient Video Coding (HEVC) is the next generation video coding standard in progress. Based on the traditional hybrid coding framework, HEVC implements enhanced tools to improve compression efficiency at the cost of far more computational payload than the capacity of real-time video applications. In this paper, we focus on the fast implementation of the HEVC encoder over modern Intel x86 processors. First, we identify the most time-consuming modules of HM 6.2 encoder, represented by motion compensation, Hadamard transform, sum of difference (SAD/SSD) calculation and integer transform. Then the single-instruction-multiple-data (SIMD) methods are exploited to optimize the computational performance of these modules. Experimental results show that in these modules the optimized encoder achieves 56% - 85% time saving compared with the HM 6.2 encoder over Intel i5-750 processor.