40 Volt NMOS in a 0.5 μm standard CMOS process

High-voltage NMOS structures were implemented by introducing a lightly doped drain area to separate the channel and the drain diffusion area for NMOS transistors, and by extending the poly layer over the intervening field oxide. Majority and minority carrier guard rings were used to minimize parasitic effects and isolate the devices. A family of high-voltage devices was implemented with various geometries in order to determine the optimal dimensions. A total of 16 square and 16 circular devices were fabricated in a 0.5 μm standard 5V CMOS technology. Measurement results demonstrate breakdown voltages as high as 40 V in comparison with 10.9 V for a standard transistor in the same run. Breakdown voltages were found to be highest for circular structures in most cases. Circular structures also showed comparable transconductance to standard transistors. Detailed characterization such as Early voltage and threshold voltage are discussed.