Efficient multi-bit SRAMs using spatial wavefunction switched (SWS)-FETs

This paper presents the multiple quantum well channel spatial wavefunction switched FETs (SWS-FETs) configured to implement multi-bit static random access memory (SRAM) cells. A 2-bit SRAM cell consists of two back-to-back connected 4-channel SWS-FETs, where each SWS-FET serves as quaternary inverter. This architecture results in reduction of FET count by 75% and data interconnect density by 50%. The designed 2-bit SRAM cell is simulated using BSIM equivalent channel models (for 25nm FETs). In addition, the binary interface logic and conversion circuitry are designed to integrate the SWS-SRAM technology. Quantum simulations for Si/Ge and InGaAs-based SWS-FETs are also presented.