A low power programmable frequency divider intended for frequency synthesizer designed in accordance with IEEE 802.15.4a standard

A low power programmable frequency divider for IEEE 802.15.4a standard is implemented in a 0.25 μm BiCMOS process. The frequency divider architecture is based on the low power high speed triple-modulus prescaler design. The triple-modulus prescaler supports three division modes (N/N±1) via the phase switching between the output signals of the master/slave emitter-coupled logic divide-by-two stage. The novel N-1 division mode is achieved by modifying the low frequency phase selection control logic. The wide division range is achieved by cascading the prescalers. In addition, the 50% duty cycle baseband clock is derived from the divider chain. The frequency of the baseband clock is equal to 499.2 MHz regardless of the chosen center frequency (in combination with the corresponding division ratio) for the multi-channel system designed for IEEE 802.15.4a standard. The measured maximum input frequencies of the divider for each of the required division ratio prove that the presented divider satisfies the specification. The measurement results demonstrate that the presented frequency divider can be used in the frequency synthesizer for generation of the center frequencies for multi-channel transceiver designed in accordance to IEEE 802.15.4a standard. The measured power dissipation of the programmable frequency divider is equal to 31.2 mW from 2.6 V supply voltage.