A 0.016-mm$^{2}$ 144-$\mu$ W Three-Stage Amplifier Capable of Driving 1-to-15 nF Capacitive Load With $> $0.95-MHz GBW

A 0.016-mm
²
144-μ W three-stage amplifier capable of driving 1-to-15-nF capacitive load (
C
_L
) is described. It is optimized via combining current-buffer Miller compensation and parasitic-pole cancellation (via an active left-half-plane zero circuit) to extend the
C
_L
drivability with small power and area. Fabricated in 0.35-μ m CMOS, the minimum gain-bandwidth product (GBW), slew rate (SR) and phase margin measured over 1-to-15-nF
C
_L
are 0.95 MHz, 0.22 V/ μs and 52.3 °, respectively. The results at 15-nF
C
_L
correspond to 2.02x-improved small-signal FOM
_S
(=GBW·C
_L
/Power), and 1.44x-improved large-signal FOM
_L
(=SR·C
_L
/Power) with respect to prior art. The sizing and optimization are systematically guided by Local Feedback Loop Analysis. It is an insightful control-centric method allowing the pole-zero placements to be more analyzable and comparable at the system level.