A 10b 1MS/s-to-10MS/s 0.11um CMOS SAR ADC for analog TV applications

This work proposes a 10b 1MS/s-to-10MS/s 0.11um CMOS SAR ADC optimizing power consumption and chip area for analog TV (NTSC/PAL) applications. The proposed DAC employs a 2-step (6b-4b) split-capacitor array with the V
CM
-based switching method for high power efficiency and small chip area. Additionally, a range-scaling technique is employed for a rail-to-rail input signal swing. The comparator accuracy is improved by offset cancellation techniques in the first-stage pre-amp. The prototype ADC in a 0.11um CMOS technology demonstrates the measured DNL and INL within 1.07LSB and 1.66LSB, respectively. The ADC shows a maximum SNDR of 54.4dB and a maximum SFDR of 69.8dB at 10MS/s, respectively. The ADC with an active die area of 0.25mm
²
consumes 2.3mW at a 1.2V and 10MS/s.