A background calibration method for DAC mismatch correction in multibit sigma-delta modulators

A topology for the calibration of DAC errors in multibit sigma delta modulators is presented. The proposed technique enables the calibration to proceed in the background. In this technique, two DACs are used in a time-interleaved fashion. One DAC is calibrated at a time while the other is connected to the modulator. The technique is demonstrated by a design in UMC 0.18 μm CMOS technology which shows a very competitive figure of merit of 78fJ/Conv-Step. The extensive simulation results are presented to validate the results.