A new validation methodology combining test and formal verification for PowerPC/sup TM/ microprocessor arrays

Test and validation of embedded array blocks remain as a major challenge in today's processor design environment. The difficulty comes from two folds. First, the sizes of the arrays are too large to be handled by the most sophisticated sequential ATPG tools. On the other hand, the complex timing and control make it hard to model these arrays as well-defined transparent blocks which combinational ATPG tools can understand. This paper describes a novel methodology for test and validation of complex array blocks in PowerPC RISC microprocessors. Unlike traditional ATPG methods, our methodology uses formal techniques to functionally verify the arrays and then derive tests from the verification results. The superiority of these tests over the traditional ATPG tests will be discussed and shown at the transistor level through experiments on various recent PowerPC array designs.