A High-Frequency Transconductance Method for Characterization of High- $\kappa$ Border Traps in III-V MOSFETs

A novel method that reveals the spatial distribution of border traps in III-V metal-oxide-semiconductor field-effect transistors (MOSFETs) is presented. The increase in transconductance with frequency is explored in a very wide frequency range (1 Hz-70 GHz) and a distributed RC network is used to model the oxide and trap capacitances. An evaluation of vertical InAs nanowire MOSFETs and surface-channel InGaAs MOSFETs with Al
₂
O
₃
/HfO
₂
high-κ gate dielectric shows a deep border-trap density of about 10
²⁰
cm
^-3
eV
^-1
and a near-interfacial trap density of about 10
²¹
cm
^-3
eV
^-1
. The latter causes an almost steplike increase in transconductance at 1-10 GHz. This demonstrates the importance of high-frequency characterization of high-κ dielectrics in III-V MOSFETs.