A self-test methodology for restructurable WSI

Progress in Wafer Scale Integration (WSI) has brought the problems of system level testing into the semiconductor manufacturing arena. Full wafer testing is complicated by the reduced controllability and observability implicit at this level of integration. Under a DARPA sponsored microelectronics research project at the University of South Florida, several monolithic WSI designs are being developed. A Standard Test Interface (STI) is included on each cell or functional module of each design. It will provide support for built-in self-test, scan based test, boundary scan test, and ad hoc module testing schemes. In addition, use of the STI standard can reduce test complexity and cost because all cells on the wafer will be tested using a single probe card. The author's WSI Standard Test Interface is based upon the proposed IEEE P1149.1 test bus standard which has been derived from the JTAG standards. It represents an extended version of the JTAG Test Access Port, and allows for simultaneous initialization, as well as individual programmability, control, and testing of all chip sites in a WSI system.<
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