A general configurable architecture for WSI implementation for neural nets

Presents a solution that allows flexible mapping of neural nets (such as multi-layered ones) onto uncommitted processing arrays in which a large number of processing elements are interconnected by a switched-bus network. The basic algorithms leading to such mapping are outlined, providing a balance between structure simplicity and parallelism of operation speed. A protocol by which the array can be configured (and, therefore, initialized) is presented: nominal operation is then described, and it is seen that the same solution providing for initialization supports also subsequent algorithms. The structure of the basic elements of the architecture (switches and processing elements) is detailed, so as to allow an evaluation of complexity as regards silicon requirements in CMOS.<
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