A high performance single chip FFT array processor for wafer scale integration

An architecture with p multiplier-adder's per butterfly stage has been developed to implement a radix p FFT. It is based on the p-fold symmetry in radix p constant geometry FFT algorithm. A methodology to realize a high radix processing element with lower radix hardware is presented. It is suitable for wafer scale integration. The latency and throughput of this architecture are evaluated. An experimental processor chip to implement a radix 2, 8 point FFT has been successfully designed in CMOS and the results are discussed.<
>