Physical Modeling of the Capacitance and Capacitive Coupling Noise of Through-Oxide Vias in FDSOI-Based Ultra-High Density 3-D ICs

Fully depleted silicon-on-insulator (FDSOI) technology boosts the opportunity to make 3-D ICs with ultrahigh integration density, due to the short and tiny through-oxide vias (TOVs), which are made after removing the entire silicon under the buried-oxide layer. This work, for the first time, develops compact physical models for the capacitance of the TOV and the coupling capacitance between the TOV and active regions in the presence of periodical power/ground lines, from fundamental electrostatic considerations. Calculation results from the models show good agreement with the simulation results from a full-3-D capacitance solver. The models are further used to analyze the threshold voltage (
V
_th
) variation in the FDSOI MOSFETs. The TOV in FDSOI and the through-silicon via (TSV) in bulk-CMOS-based 3-D ICs are finally compared in terms of the self-impedance as well as their impact on MOSFET
V
_th
variation through capacitive noise coupling. These results provide important insights to TOV/TSV design and optimization in emerging 3-D ICs.