C-based PLC to FPGA translation and implementation: The effects of coding styles

PLCs have been the first choice for automation engineers for fast, reliable and robust implementation of their control algorithms for many years. Recently, with the introduction of advanced MEMS sensors and actuators and the penetration of new technologies in many diverse everyday tasks, with complicated control mechanisms and advanced calculations, it has been made clear that traditional PLCs need a technology boost. This boost can be offered by modern FPGA devices so a number of automated or semi-automated translating methodologies from PLC to FPGA have been proposed. This paper presents the effects of coding styles in a translation methodology using C-based hardware design and the corresponding high-level synthesis toolset. As it is shown, C-based hardware design offers optimization opportunities for floating point calculations not found in traditional HDL-based hardware design, provided specific coding guidelines are followed. These guidelines are integrated in a systematic translation methodology and their effects are compared to the effects of architectural optimizations offered by high-level synthesis. As shown in the experimental results, algorithmic optimizations (coding styles) clearly outperform architectural optimizations and so, their use is highly recommended for the development of next generation FPGA based controllers.