High-Performance Computing Based on Heterogeneous and Reconfigurable Architectures

This paper aims to describe a proposal of a reconfigurable and heterogeneous computing architecture for digital signal processing on embedded systems, based on the cooperative code execution between DSP (Digital Signal Processor) and FPGAs (Field-Programmable Gate Arrays). In order to validate this approach, some scenarios has been developed for processing using FFT (Fast Fourier Transform) and DCT (Discrete Cosine Transform) algorithm, which has been one of the main module used for digital image compression and also is applied in several coding schemes, such as JPEG, MPEGx and H.26x.