An Ultra-Low Power Asynchronous-Logic In-Situ Self-Adaptive $V_{\rm DD}$ System for Wireless Sensor Networks

We propose a Sub-threshold (Sub-
V
_t
) Self-Adaptive
V
_DD
Scaling (SSAVS) system for a Wireless Sensor Network with the objective of lowest possible power dissipation for the prevailing throughput and circuit conditions, yet high robustness and with minimal overheads. The effort to achieve the lowest possible power operation is by means of adjusting
V
_DD
to the minimum voltage (within 50 mV) for said conditions. High robustness is achieved by adopting the Quasi-Delay-Insensitive (QDI) asynchronous-logic protocols where the circuits therein are self-timed, and by the embodiment of our proposed Pre-Charged-Static-Logic (PCSL) design approach; when compared against competing approaches, the PCSL is most competitive in terms of energy/operation, delay and IC area. By exploiting the already existing request and acknowledge signals of the QDI protocols, the ensuing overhead of the SSAVS is very modest. The filter bank embodied in the SSAVS is shown to be ultra-low power and highly robust. When benchmarked against the competing conventional Dynamic-Voltage-Frequency-Scaling (DVFS) synchronous-logic counterpart, no one system is particularly advantageous when the operating conditions are known. However, when the competing DVFS system is designed for the worst-case condition, the proposed SSAVS system is somewhat more competitive, including uninterrupted operation while its
V
_DD
self-adjusts to the varying conditions.