Modeling and design of FETs in the temperature range from -50/spl deg/C to +120/spl deg/C oriented to low-power GaAs ICs CAD applying low-frequency design techniques

In this paper more efficient thermal design rules combined with an automatic procedure to determine the optimal layout for thermal effect optimization and new improved large/small signal thermal models of GaAs FETs are proposed. The small signal model is available also in the polynomial form required for thermal CAD of low-power MMICs, with low frequency ICs design technique based on physical parameters of the foundry. Therefore, a large signal thermal model of the device is developed which is very accurate in the range of temperature from about -50/spl deg/C to +120/spl deg/C and subsequently, the SSECPs (Small Signal Equivalent Circuit Parameters) expressions are determined in the previous polynomial form. The approach to define the new models is based on physical considerations concerning the thermal effects, necessary to achieve a reliable design, in spite of their non-physical nature.