AToM: the front-end chip for the BaBar silicon vertex tracker detector

This paper describes the readout integrated circuit of the silicon vertex tracker detector for the BaBar experiment at Stanford Linear Accelerator Center. A unique feature of the circuit is its ability to simultaneously amplify and shape signals from 128 microstrip detectors, retain the charge information during the level 1 trigger latency time, and perform sparsification and data transmission over a single serial line. The circuit is composed of two sections. In the analog section signals from the detectors are amplified through a charge sensitive loop, shaped by a CR-RC/sup 2/ filter with digitally selectable peaking time (100 ns, 200 ns, 300 ns or 400 ns) and finally compared to a digitally selectable threshold to perform a range compression. The digital section contains a 193 deep digital pipeline, a three level back-end buffer, two DACs for threshold and calibration voltages, a global control section and a command decoder. The digital section operates at 60 MHz clock speed. Noise measurements at 200 ns peaking time and 3.5 mW total power dissipation per channel yield an equivalent noise charge of 600 el. rms at 12 pF added source capacitance. The chip measures 5.7 mm/spl times/8.3 mm and contains 330 K transistors. A full-scale prototype was fabricated in a 0.8 /spl mu/m, 3-metal rad-soft CMOS process, a second prototype has been characterized using a compatible rad-hard process by Honeywell and the pre-production chip is currently being fabricated.