A 2.5 V 50 MHz IF-sampling /spl Delta//spl Sigma/-modulator for digital cellular telephones

This paper discusses the design of a 50 MHz IF-sampling switched-capacitor /spl Delta//spl Sigma/-modulator with a 2.5 V supply voltage implemented in a 0.5 /spl mu/m BiCMOS process. The problems caused by the low analog supply voltage are addressed with special biasing and common-mode arrangements. Simulation results verifying a peak SNDR of 83 dB for a baseband signal are presented.