Direct Polish STI HSS CMP with Improved Planarity and Defect Performance

Shallow Trench Isolation (STI) is widely used for transistor isolation in advanced semiconductor devices. The main advantage STI offers is that it enables higher packing density, planar topography, and lower cost compared to conventional processes. Silicon dioxide, which is used for trench isolation, is deposited using a subatmospheric chemical vapor deposition (SACVD) technique known as high aspect ratio process (HARP(TM)). Chemical Mechanical Planarization (CMP) is used to remove the excess topography and achieve device level planarization. Applied Materials- Reflexion(r) LK CMP systems have been widely used to develop direct polish STI CMP process using ceria-based high-selective slurry (HSS). The focus of the present work has been to evaluate new consumable sets for the direct polish HSS STI CMP process. By using the optimal combination of polishing pad, pad conditioner disk, and HSS, significant improvement in planarity and defect performance was achieved. Furthermore the improved process results in improved throughput using the Reflexion(r) LK CMP system. The results indicate that Applied Materials Reflexion(r) LK system can be used to meet the performance metrics of advanced semiconductor devices. Keywords: CMP, direct-polish STI, ceria slurry, high selective slurry, HSS, HARP(TM), Scratches