Employing radiation hardness by design techniques with commercial integrated circuit processes

Though process hardening remains the preferred method for achieving radiation hardness in high density integrated circuits (ICs), recent investigations into the hardness of specially designed gate array cells fabricated in a commercial 0.81 /spl mu/m CMOS fabrication process have demonstrated greater than 100 krads (Si) total ionizing dose hardness, no single event latchup, and single event upset LET (linear energy transfer) (LET) thresholds greater than 50 MeV-cm/sup 2//mg. This work suggests that it is possible to achieve inexpensive ASICs (Application Specific Integrated Circuits) of modest complexity and radiation tolerance with commercial IC processes.