64 Mbit SOI-DRAM technologies using body-contacted (BC) structure

Summary form only given. Recently, DRAMs using SOI substrates have been widely needed because of their inherent high speed low power characteristics due to small junction capacitances. However, the floating body effect is the most serious problem. The floating body can cause dynamic retention time problems in DRAMs, and a leakage problem due to a small drain-to-source breakdown voltage. In this work, a Body-Contacted (BC) SOI MOSFET structure with no floating body effect is successfully applied to a 64M SOI DRAM. The layout, process steps and the operation voltage are completely compatible with the bulk MOSFET process. We evaluated the transistor characteristics and the chip performances.