A 50–70GHz frequency doubler in 90nm CMOS

This paper presents the design and measurement of a V-band frequency doubler in 90nm IBM CMOS process. The doubler employs active multiplying architecture to generate harmonics of input fundamental signal, and distributed passive microstrip line to suppress unwanted signals. This doubler has the advantage of low power consumption, relatively low conversion loss, and simple topology for circuit design. The measured conversion loss is less than 11dB in a broad band frequency from 50 to 70GHz. The total DC power dissipation of this doubler is 4.5mW, and the chip size including pads is 0.4mm
²
.