Floorplan optimization on multiprocessors

A parallel formulation of a branch-and-bound algorithm for floorplan optimization in VLSI design is given. Implementation details and performance analyses of the authors' formulation are presented. This implementation was done on a 128-node Symult s2010 multicomputer, as well as on a network of 16 SUN workstations. In the experiments with realistic problems, linear speedups on both machine configurations were obtained. Previous analyses of a similar parallel algorithm suggest that linear speedup can be obtained even on very large computers (>1000 processors) on practical instances of this problem.<
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