Motion estimation VLSI architecture for image coding

Special-purpose chips based on highly parallel architectures, for possible use in videophone, videoconference, digital TV distribution and HDTV codecs, are considered. Functional interface specifications for a motion estimator to be inserted in a coder system are detailed. The range of possible operative part-kernel architectures is derived, based on formal high-level synthesis methods. A novel implementation using redundant base 2 digital-serial arithmetic is presented, resulting in a compact (70000 transistors) motion estimation VLSI block.<
>