Area Utilization Based Mapping for Network-on-chip Architectures with Over-sized IP Cores

Network-on-chip (NoC) architectures have been recently proposed as the communication framework for large-scale chips. A well-designed NoC architecture can facilitate the IP cores to communicate with each other efficiently. In this paper, we propose a systematic mapping scheme, called area utilization based mapping (AUBM), to map the IP cores from the communication core graph to the mesh network. In AUBM, the IP cores can be of various sizes. Extensive experiments have been conducted for evaluating the mapping schemes. AUBM is compared with previously proposed schemes for different applications as well as synthetic workloads. Our experiment results show that AUBM outperforms others in almost all cases in terms of the mapping cost involving traffic volume and chip area.