MSXmin: a self-routing multicast ATM packet switch with O(log/sup 2/N) delay and O(N log/sup 2/N) hardware complexity

We propose and analyze the architecture for a large scale high-speed multicast switch called MSXmin. The hardware complexity of MSXmin is O(Nlog/sup 2/N) which compares favorably with existing architectures. Further, the internal latency of the MSXmin is O(log/sup 2/N) bits. While it is superior to the existing architectures in terms of the hardware complexity and the internal latency, it is comparable to other multicast switches in terms of the header overhead and translation table complexity. MSXmin is output buffered and based on the group knockout principle. Moreover, MSXmin is a dual-bit controlled tree-based switch.