Design and implementation of a near maximum likelihood decoder for Cortex codes

Cortex codes are an emerging family among the rate-1/2 self-dual systematic linear block codes with good distance properties. This paper investigates the challenging issue of designing an efficient Maximum Likelihood (ML) decoder for Cortex codes. It first reviews a dedicated architecture that takes advantage of the particular structure of this code to simplify the decoding. Then, we propose a technique to improve the architecture by the generation of an optimal list of binary vectors. An optimal stopping criterion is also proposed. Simulation results show that the proposed architecture achieves an excellent performance/complexity trade-off for short Cortex codes. The proposed decoder architecture has been implemented on an FPGA device for the (24,12,8) Cortex code. This implementation supports an information throughput of 300 Mb/s. At a signal-to-noise ratio Eb/No=8 dB, the Bit Error Rate equals 2 × 10
^-10
, which is close to the performance of the Maximum Likelihood decoder.