Standard cell VLSI design: A tutorial

Many of today's high technology products require low-cost implementation and short development times. Designers are faced with the dilemma of cranking out designs quickly that are inexpensive and work the first time. Careful economic trade-offs will have to be made between the level of integration, choice of technology, packaging or lack thereof (i.e., surface mount), and the ability to meet a market window. The standard cell approach to VLSI design fits into the overall custom VLSI family as a cheaper/timely alternative to gate arrays and fully custom approaches. Although it had its origins in the trouble-free design of medium-speed digital circuitry, advances in routing techniques have made this technology easily extendable to the analog realm, making it relatively painless to implement the analog and digital VLSI circuitry of the present. In addition, the use of standard cells provide an easy method of utilizing earlier wisdom and avoids reinventing the “wheel.” The slight penalty in area suffered compared to fully custom approaches is increasingly diminishing with finer line-width technologies and smarter routing programs. As compared with a full custom implementation, standard cells offer shorter schedules and usually work on the first turnaround. The authors believe that in the very near future, design costs will force most IC designs to go this route with the exception of a few high volume runners. This tutorial will cover the design aspects and methodology from concept to manufacture of standard cell VLSI circuits. It will attempt to provide a broad brush treatment of the subject and show what design aids are available to help designers get their jobs done efficiently and reliably. This tutorial will intentionally not be overly technical and will instead be directed toward the new VLSI designer and hopefully be a starting base of knowledge to be expanded with experience.