A fast hybrid DCT architecture supporting H.264, VC-1, MPEG-2, AVS and JPEG codecs

The paper presents a hybrid algorithm to compute the 8×8 Integer Inverse Discrete Cosine Transform (IDCT) of multiple modern codecs - AVS, VC-1, H.264/AVC, JPEG and MPEG-2. Based on the symmetric structure of the matrices and the similarity in matrix operation, we develop a factorizing algorithm to compute the 8×8 IDCT of first three standards. To reduce the hardware complexities we implement the last two standards by delta mapping scheme from the architecture of VC-1. The combination of these two hardware share approach ensures the maximum circuit reuse during the computation. The entire architecture is designed with only adders and shifters to reduce the hardware cost significantly. The design is implemented on FPGA and later synthesized in CMOS 0.18um technology. The results meet the requirements of modern day's super resolution video coding applications.