Modelling of losses in load harmonic networks of high efficiency class E power amplifiers

To obtain high efficiency of dc to ac power conversion in an amplifier, it is necessary to decrease the power dissipation in the active device by ensuring that, the overlap of the voltage and current waveforms at the output terminals of the active device is minimized. This reduction of overlap is obtained by using load harmonic networks to shape the above waveforms at the output terminals of the active device. In the three common classes of high efficiency power amplifiers (PAs) (F. F
^-1
and E), this shaping is obtained by attenuating different harmonics of the waveforms by using load harmonic networks. For the class E amplifier a capacitance is placed across at the output terminals of the active device. This is to ensure that the output voltage is delayed until the active device is turned `off' and the output voltage reaches its minimum value with a slow turn `on'. If this device is driven hard 'on' and 'off' to obtain high efficiency it is shown that the input impedance must be very high at the harmonic frequencies. At the design frequency the required input impedance depends on the value of the above capacitance. Ideal lossless transmission lines (Tlines) are used in the initial design of harmonic networks for high efficiency power amplifiers and then practically realised using microstrip lines (Mlines). As the metal and substrate losses in Mlines are normally expressed in terms of attenuation constants, these losses are difficult determine as they require solutions of complex mathematical equations. In this paper to reduce such complex analysis the losses in an Mlines are modelled as a Tlines in series a resistance. A novel method is proposed to determine this resistance as a function of the length of the Mlines which is realised using inexpensive PCB FR4 substrate. Then for the above two line models, ha