SPRINT: Scalable photonic switching fabric for high-performance computing (HPC)

High-performance computing systems and datacenters will interconnect hundreds to thousands of heterogeneous general purpose or specialized cores in the future. As the number of network end-point sockets scales exponentially, the underlying communication fabric must deliver high bandwidth with low power and reduced switching complexity. While high-radix routers enable smaller diameter networks, the penalty is in increased switching complexity and router power. In this paper, we propose SPRINT (scalable photonic reconfigurable interconnect), which can scale to a large number of cores using photonic switching implemented with silicon micro-ring resonators (MRRs). MRRs are low power, high bandwidth photonic switching devices that can be arranged to function similarly to a high-radix router with reduced complexity and power. We will first show the design of a 64 core cluster using optical interconnects and electrical packet switching. To build scalable switching crossconnects, we investigate the design of 256-, 512- and 1024-socket versions of SPRINT connected to function as passive arrayed-waveguide gratings. Our proposed switching crossconnect with single and dual micro-rings minimizes the hop count to 4 for a 1024 core network while reducing the power dissipation, increasing the bandwidth and reducing the switching complexity.