Architecture of a multiprocessor system with embedded DRAM for large area integration

The architecture of a MIMD-based multiprocessor system for video coding applications is presented. It consists of a number of identical bus-connected processors, each specifically adapted to video coding algorithms and equipped with an embedded DRAM for storage of image data. Each of the images to be processed is statically segmented into rectangular fields, which are distributed among the processors. The processors perform the complete set of coding or decoding tasks on the assigned portion of the image. Because each processor is equipped with sufficient memory for image storage and processing power, no additional external hardware is required. The architecture of each processor and embedded DRAM is designed for large area integration. This allows the implementation of a complex video coding system on a single chip.